This invention relates to a data processing (DP) system capable of processing a plurality of instructions simultaneously (hereunder referred to as "pipeline-controlled DP system").
A conventional pipeline-controlled (PC) DP system is equipped with an execution unit consisting of a plurality of subunits, each of which can accomplish the high-speed operation for a given simple process of plural instructions. More specifically, each subunit is processing one or another part of a certain instruction at a given time, so that the execution unit can process such instructions simultaneously. However, since each execution of all the instructions over the whole subunits is done sequentially, the entire processing time becomes increasingly long.
For details of such a PC DP system, reference is made to an article entitled "The IBM System/360 Model 91: Machine Philosophy and Instruction Handling" by D. W. Anderson et al, IBM Journal of Research and Development, Vol. 11, No. 1, pp. 8-24, January issue, 1967 (Reference 1).
To solve such a disadvantage in the system shown in Reference 1, another type of PCDP system, in which all instructions are processed in parallel, is proposed in an article entitled "An Efficient Algorithm for Exploiting Multiple Arithmetic Units" by R. M. Tomasulo, IBM Journal of Research and Development, Vol. 11, No. 1, pp. 25-33, January issue, 1967 (Reference 2). With this proposed system, however, complicated control and hardware are inevitably needed.